1. Field of the Invention
This invention relates generally to packaging and more particularly to packaging of semiconductor slices or wafers.
2. Description of the Prior Art
In the semiconductor art, numbers of complex circuits are formed in slices or wafers of semiconductor materials. These wafers are then broken or diced into individual circuits or chips which are subsequently packaged. Such packaging of individual chips is well known and has been well eveloped. Packages suitable for containing a large quantity of integrated circuit chips are known to the art and diclosed for example in U.S. Pat. No. 3,529,213 to W. A. Farrand, et al. Another example of the packaging structure providing for a multiplicity of hermetically sealed modules for integrated circuit chips and incorporating cooling is disclosed in U.S. Pat. No. 3,706,010 to L. Laermer et al.
The use of liquid cooling for dissipating heat generated by the operation of the integrated circuit chips is disclosed in the commonly assigned U.S. Pat. No. 3,537,063 to P. E. Beaulieu.
While the density of semiconductor circuits has greatly increased over the past years, the packaging of these integrated circuits has failed to keep up with the increase of circuit density, for while packaging of individual chips containing such circuits has been well developed little or no attention has been given to packages which maximize the density of the packaging of such semiconductor circuits.
Alternative approaches to the same problems are described in a patent application, Ser. No. 462,461, by A. A. Rifkin et al entitled "An Electronic Assembly for Wafer Circuit Elements" and a patent application, Ser. No. 462,463, by D. W. Skinner entitled "A Wafer Circuit Package" both assigned to the assignee of this application and filed on even date herewith.